Memory Systems and I/O

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reading · we frame, you read MIT or the canonical taught · we author, no canonical fits ↺ spirals back to earlier lessons

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Complete Digital Logic and Computer Organization (Nand2Tetris + Theory) first.

This course unlocks once you've finished its prerequisite. Open prerequisite →

Prerequisites

Digital Logic and Computer Organization (Nand2Tetris + Theory) not yet

Complete prerequisites first to enroll.

reading · 30 min + ~210 min canonical

Cache Performance and Replacement Policies: When the Cache Is Full

In the last course you learned what a cache is — a small fast memory that keeps hot data close, organised as direct-mapped, set-associative, or fully-associative slots. This lesso…

primary Nand2Tetris (continued)

preview →

reading · 35 min + ~210 min canonical L1

Virtual Memory: Page Tables, the TLB, and the Great Illusion

Here is a thing you have relied on your entire career without being told it was a trick: every program on your machine believes it owns all of memory, starting at address zero, al…

primary Nand2Tetris (continued)

after L1 locked

reading · 30 min + ~210 min canonical L1

I/O Systems: Polling, Interrupts, and DMA

Everything so far in this course happened inside the box — gates, the ALU, registers, caches, memory. But a computer that can't talk to the outside world is a very fast paperweigh…

primary Nand2Tetris (continued)

after L2 locked

reading · 30 min + ~210 min canonical L1

Storage Devices and RAID: Disks, SSDs, and the Physics of Persistence

At the bottom of the memory hierarchy is the tier that survives a power cut — storage. And storage is where computing stops being pure logic and runs headlong into physics. A spin…

primary Nand2Tetris (continued)

after L3 locked

exercise reading · 15 min L1

Exercises: Easy (Warm-up)

- [ ] Calculate cache parameters — Given 32KB cache, 64B blocks, 4-way: compute sets, tag/index/offset bits - [ ] Draw the memory hierarchy with latency numbers — Registers (1ns) …

after L4 locked

exercise reading · 30 min L1

Exercises: Medium (Core)

- [ ] Implement LRU cache eviction in C — Doubly-linked list + hash map, simulate cache behavior - [ ] Implement a page table walker in C — Two-level page table, translate virtual…

after L5 locked

exercise reading · 45 min L1

Exercises: Hard (Stretch)

- [ ] Implement a TLB simulator in C — Associative lookup, LRU replacement, miss penalty calculation - [ ] Analyze Belady's anomaly — Find a reference string where FIFO with more …

after L6 locked

exercise reading · 60 min L1

Mini-Project

- [ ] Build a cache simulator in C — Configurable direct-mapped/set-associative/fully-associative, LRU/FIFO eviction, read trace files, report hit rate and miss rate statistics

after L7 locked

project reading · 480 min L1

Project: Cache Simulator in C

Implement a configurable cache simulator: direct-mapped, N-way set-associative, and fully-associative. Support LRU and FIFO eviction. Read memory access traces and report hit rate…

after L8 locked

L10

project reading · 360 min L1

Project: Hack Assembler in Ruby

Write an assembler for the Hack assembly language (Nand2Tetris Project 6). Parse assembly mnemonics, resolve symbols, generate binary machine code. This bridges the hardware (Proj…

after L9 locked

L11

assessment reading · 56 min L1

Self-Assessment: Memory Systems and I/O

- [ ] Describe the memory hierarchy from registers to disk. What are typical latencies at each level? - [ ] What is a cache? Explain direct-mapped, set-associative, and fully-asso…

after L10 locked

L12

assessment reading · 60 min L1

Quarter 5 Gate Check: Computer Architecture

- [ ] Course 5.1 knowledge check passed - [ ] Course 5.2 knowledge check passed - [ ] Nand2Tetris Computer capstone completed (Projects 1-6)

after L11 locked

12 lessons. Read in order; spiral back when you need to. By the end you'll have used the core ideas twice — once on the abstract, once on something you'll meet at work next week.